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122 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide
1-800-255-7778 UG018 (v2.0) August 20, 2004
Chapter 2: Input/Output Interfaces
R
);
end component
begin
-- Component Instantiation
U_PPC1 : PPC405
port map (
...
JTGC405TCK => TCK_IN,
JTGC405TDI => TDI_IN,
JTGC405TMS => TMS_IN,
JTGC405TRSTNEG => TRSTNEG_IN,
C405JTGTDO => TDO_OUT,
JTGC405BNDSCANTDO => open,
C405JTGTDOEN => open,
C405JTGEXTEST => open,
C405JTGCAPTUREDR => open,
C405JTGSHIFTDR => open,
C405JTGUPDATEDR=> open,
C405JTGPGMOUT=> open,
...
);
end SINGLE_PPC_JTAG_INDIVIDUAL_arch;
// Module: SINGLE_PPC_JTAG_INDIVIDUAL
// Description: Verilog instantiation template for individual
// connection of a single PPC405 core to user I/O
module SINGLE_PPC_JTAG_INDIVIDUAL (
TCK_IN,
TDI_IN,
TMS_IN,
TRSTNEG_IN
TDO_OUT
);
input TCK_IN;
input TDI_IN;
input TMS_IN;
input TRSTNEG_IN;
output TDO_OUT;
// Component Instantiation
PPC405 U_PPC1(
...
.JTGC405TCK (TCK_IN),
.JTGC405TDI (TDI_IN),
.JTGC405TMS (TMS_IN),
.JTGC405TRSTNEG (TRSTNEG_IN),
.C405JTGTDO (TDO_OUT),
.JTGC405BNDSCANTDO (),
.C405JTGTDOEN (),
.C405JTGEXTEST (),
.C405JTGCAPTUREDR (),