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PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 91
UG018 (v2.0) August 20, 2004 1-800-255-7778
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DSPLB Three Consecutive Word Writes
The timing diagram in Figure 2-22 shows three consecutive word writes. It provides an
example of the fastest speed at which the DCU can request and send single words over the
PLB. The word writes could be in response to non-cacheable stores, cacheable stores to
write-through memory, or cacheable stores that do not allocate a cache line. Consecutive
writes cannot be address pipelined between the DCU and BIU.
The first word write (ww1) is requested by the DCU in cycle 2. The BIU responds in the
same cycle the request is made by the DCU. A single word is sent from the DCU to the BIU
in cycle 2. The BIU uses the byte enables to select the appropriate bytes from the write-data
bus.
The second word write (ww2) is requested after the first write is complete. The DCU
makes the request in cycle 4 and the BIU responds in the same cycle. A single word is sent
from the DCU to the BIU in cycle 4. The BIU uses the byte enables to select the appropriate
bytes from the write-data bus.
The third word write (ww3) is requested after the second write is complete. The DCU
makes the request in cycle 6 and the BIU responds in the same cycle. A single word is sent
from the DCU to the BIU in cycle 6. The BIU uses the byte enables to select the appropriate
bytes from the write-data bus.
Figure 2-21: DSPLB Line Write/Word Write/Line Write
Cy cle
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
PLBCLK and CPMC405CLK
UG018_25_101701
PPC405 Outputs:
C405PLBDCUREQUEST
C405PLBDCURNW
C405PLBDCUABUS[0:31]
adr1 adr2 adr3
flush1 flush3
C405PLBDCUBE[0:7]
C405PLBDCUWRDBUS[0:63]
C405PLBDCUSIZE2
DCU
ww2 wl3wl1
d1
01
d1
23
d1
45
d1
67
d2
d3
01
d3
23
d3
45
d3
67
PLB/BIU Outputs:
PLBC405DCUADDRACK
PLBC405DCURDDBUS[0:63]
PLBC405DCURDWDADDR[1:3]
PLBC405DCURDDACK
PLBC405DCUWRDACK
PLBC405DCUBUSY
ww2 wl3wl1
wl1
01
wl1
23
wl1
45
wl1
67
ww2 wl3
01
wl3
23
wl3
45
wl3
67
val