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74 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide
1-800-255-7778 UG018 (v2.0) August 20, 2004
Chapter 2: Input/Output Interfaces
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If the transfer size is a single word, C405PLBDCUBE[0:7] is also valid when the request is
asserted. These signals specify which bytes are transferred between the DCU and PLB
slave. If the transfer size is an eight-word line, C405PLBDCUBE[0:7] is not used and must
be ignored by the PLB slave.
C405PLBDCUPRIORITY[0:1] is valid when the request is asserted. This signal indicates
the priority of the data-access request. It is used by the PLB arbiter to prioritize
simultaneous requests from multiple PLB masters.
The DCU supports up to three outstanding requests over the PLB (two reads and one
write). The DCU can make a subsequent request after the current request is acknowledged.
The DCU deasserts C405PLBDCUREQUEST for at least one cycle after the current request
is acknowledged and before the subsequent request is asserted.
If the PLB slave supports address pipelining, it must respond to multiple requests in the
order they are presented by the DCU. All data associated with a prior request must be
transferred before any data associated with a subsequent request is transferred. Multiple
write requests are not pipelined. The DCU does not present a second write request until at
least two cycles after the last write acknowledge (PLBC405DCUWRDACK) is sent from the
PLB slave to the DCU, completing the first request.
The DCU only aborts a data-access request if the processor is reset. The DCU removes a
request by asserting C405PLBDCUABORT while the request is asserted. In the next cycle
the request is deasserted and remains deasserted until after the processor is reset.
C405PLBDCURNW (Output)
When asserted, this signal indicates the DCU is making a read request. When deasserted,
this signal indicates the DCU is making a write request. This signal is valid when the DCU
is presenting a data-access request to the PLB slave. The signal remains valid until the cycle
following acknowledgement of the request by the PLB slave. (The PLB slave asserts
PLBC405DCUADDRACK to acknowledge the request.)
C405PLBDCUABUS[0:31] (Output)
This bus specifies the memory address of the data-access request. The address is valid
during the time the data-access request signal (C405PLBDCUREQUEST) is asserted. It
remains valid until the cycle following acknowledgement of the request by the PLB slave
(the PLB slave asserts PLBC405DCUADDRACK to acknowledge the request).
C405PLBDCUSIZE2 indicates the data-access transfer size. If an eight-word transfer size is
used, memory-address bits [0:26] specify the aligned eight-word cache line to be
transferred. If a single word transfer size is used, the byte enables (C405PLBDCUBE[0:7])
specify which bytes on the data bus are involved in the transfer.
C405PLBDCUSIZE2 (Output)
This signal specifies the transfer size of the data-access request. When asserted, an eight-
word transfer size is specified. When deasserted, a single word transfer size is specified.
This signal is valid when the DCU is presenting a data-access request to the PLB slave. The
signal remains valid until the cycle following acknowledgement of the request by the PLB
slave. (The PLB slave asserts PLBC405DCUADDRACK to acknowledge the request.)
A single word transfer moves one to four consecutive data bytes beginning at the memory
address of the data-access request. For this transfer size, C405PLBDCUBE[0:7] specifies
which bytes on the data bus are involved in the transfer.