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38 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide
1-800-255-7778 UG018 (v2.0) August 20, 2004
Chapter 2: Input/Output Interfaces
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CPMC405TIMERTICK (Input)
This signal is used to control the update frequency of the PowerPC 405 time base and PIT
(the FIT and WDT are timer events triggered by the time base). The time base is
incremented and the PIT is decremented every cycle that CPMC405TIMERTICK and
CPMC405CLOCK are both active. CPMC405TIMERTICK should be synchronous with
CPMC405CLOCK for the timers to operate predictably. The timers are updated at the
PowerPC 405 clock frequency if CPMC405TIMERTICK is held active.
CPMC405SYNCBYPASS (Input, Virtex-4-FX Only)
Allows the user to bypass the PLB synchronization module inside the PowerPC core and
instead use a Virtex-II Pro compatible synchronizer in the processor block. When this
signal is enabled, integer clock ratios between 1:1 and 16:1 are possible. If disabled, the user
can use fractional clock ratios of N/2 and N/3 for any integer N, but must also ensure that
PLB and CPU clocks are rising-edge aligned, and accept additional latency for the
synchronization.
CPMDCRCLK (Input, Virtex-4-FX Only)
This is the DCR interface clock used by the PPC to synchronize communication between
the PowerPC’s internal clock domain (CPMC405CLOCK) and the DCR bus transactions
performed using the DCR slave clocks. The PowerPC core to DCR interface clock ratio can
be any integer between 1:1 and 16:1. Clocks must be rising-edge aligned.
CPMFCMCLK (Input, Virtex-4-FX Only)
This is the re-synchronization clock for transactions between the APU controller and an
FCM. Allows the APU controller internally to run at the CPMC405CLOCK speed,
independently of the FCM interface transaction speed. CPMFCMCLK would typically be
the same clock that clocks the FCM internally. PowerPC core to FCM interface clock ratio
can be any integer between 1:1 and 16:1. Clocks must be rising-edge aligned.
C405CPMMSREE (Output)
This signal indicates the state of the MSR[EE] (external-interrupt enable) bit. When
asserted, external interrupts are enabled (MSR[EE]=1). When deasserted, external
interrupts are disabled (MSR[EE]=0). The CPM can use this signal to wake the processor
from sleep mode when an external noncritical interrupt occurs.
When the processor wakes up, it deasserts the C405CPMMSREE, C405CPMMSRCE, and
C405CPMTIMERIRQ signals one processor clock cycle before it deasserts the
C405CPMCORESLEEPREQ signal. Consequently, the CPM should latch the
C405CPMMSREE, C405CPMMSRCE, and C405CPMTIMERIRQ signals before using them
to control the processor clocks.
C405CPMMSRCE (Output)
This signal indicates the state of the MSR[CE] (critical-interrupt enable) bit. When asserted,
critical interrupts are enabled (MSR[CE]=1). When deasserted, critical interrupts are
disabled (MSR[CE]=0). The CPM can use this signal to wake the processor from sleep
mode when an external critical interrupt occurs.
When the processor wakes up, it deasserts the C405CPMMSREE, C405CPMMSRCE, and
C405CPMTIMERIRQ signals one processor clock cycle before it deasserts the
C405CPMCORESLEEPREQ signal. For this reason, the CPM should latch the