Filter
Top Products
126 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide
1-800-255-7778 UG018 (v2.0) August 20, 2004
Chapter 2: Input/Output Interfaces
R
component JTAGPPC
port(
TDOTSPPC : in std_logic;
TDOPPC : in std_logic;
TMS : out std_logic;
TDIPPC : out std_logic;
TCK : out std_logic;
);
end component;
signal TDO_TS_PPC : std_logic;
signal TMS_PPC : std_logic;
signal TDI_PPC : std_logic;
signal TCK_PPC : std_logic;
signal TDO_OUT1 : std_logic;
signal TDO_OUT2 : std_logic;
signal TDO_TS_OUT1 : std_logic;
signal TDO_TS_OUT2 : std_logic;
begin
TDO_TS_PPC <= TDO_TS_OUT1 OR TDO_TS_OUT2;
-- Component Instantiation
U_PPC1 : PPC405
port map (
...
JTGC405TCK => TCK_PPC,
JTGC405TDI => TDI_PPC
JTGC405TMS => TMS_PPC
JTGC405TRSTNEG => 1,
C405JTGTDO => TDO_OUT1,
JTGC405BNDSCANTDO => open,
C405JTGTDOEN =>TDO_TS_OUT1;
C405JTGEXTEST => open,
C405JTGCAPTUREDR => open,
C405JTGSHIFTDR => open,
C405JTGUPDATEDR=> open,
C405JTGPGMOUT=> open,
...
);
U_PPC2 : PPC405
port map (
...
JTGC405TCK => TCK_PPC,
JTGC405TDI => TDO_OUT1,
JTGC405TMS => TMS_PPC,
JTGC405TRSTNEG => 1,
C405JTGTDO => TDO_OUT2,
JTGC405BNDSCANTDO => open,
C405JTGTDOEN => TDO_TS_OUT2,
C405JTGEXTEST => open,
C405JTGCAPTUREDR => open,
C405JTGSHIFTDR => open,
C405JTGUPDATEDR=> open,
C405JTGPGMOUT=> open,
...
);