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90 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide
1-800-255-7778 UG018 (v2.0) August 20, 2004
Chapter 2: Input/Output Interfaces
R
The third line write (wl3) cannot be started until the second request (wl2) is complete. This
request is made by the DCU in cycle 13 in response to the flush3 request. The BIU responds
in the same cycle the request is made by the DCU. Data is sent from the DCU to the BIU in
cycles 13 through 16.
DSPLB Line Write/Word Write/Line Write
The timing diagram in Figure 2-21 shows a sequence involving an eight-word line write, a
word write, and another an eight-word line write. Consecutive writes cannot be address
pipelined between the DCU and BIU. The line writes are cacheable. The word writes could
be in response to non-cacheable stores, cacheable stores to write-through memory, or
cacheable stores that do not allocate a cache line.
The first line write (wl1) is requested by the DCU in cycle 3 in response to a cache flush
(represented by the flush1 transaction in cycles 1 through 2). The BIU responds in the same
cycle the request is made by the DCU. Data is sent from the DCU to the BIU in cycles 3
through 6.
The word write (ww2) cannot be started until the first request is complete. This request is
made by the DCU in cycle 8 and the BIU responds in the same cycle. A single word is sent
from the DCU to the BIU in cycle 8. The BIU uses the byte enables to select the appropriate
bytes from the write-data bus.
The DCU queues the second flush request, flush3. The second line write (wl3) cannot be
started until the second request (ww2) is complete. This request is made by the DCU in
cycle 10 in response to the flush3 request. The BIU responds in the same cycle the request
is made by the DCU. Data is sent from the DCU to the BIU in cycles 10 through 13.
Figure 2-20: DSPLB Three Consecutive Line Writes
Cy cle
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
PLBCLK and CPMC405CLK
UG018_24_101701
PPC405 Outputs:
C405PLBDCUREQUEST
C405PLBDCURNW
C405PLBDCUABUS[0:31]
adr1 adr2 adr3
flush1 flush2 flush3
C405PLBDCUBE[0:7]
C405PLBDCUWRDBUS[0:63]
C405PLBDCUSIZE2
DCU
wl2 wl3wl1
d3
01
d3
23
d3
45
d3
67
d2
01
d2
23
d2
45
d2
67
d1
01
d1
23
d1
45
d1
67
PLB/BIU Outputs:
PLBC405DCUADDRACK
PLBC405DCURDDBUS[0:63]
PLBC405DCURDWDADDR[1:3]
PLBC405DCURDDACK
PLBC405DCUWRDACK
PLBC405DCUBUSY
wl2 wl3wl1
wl1
01
wl1
23
wl1
45
wl1
67
wl2
01
wl2
23
wl2
45
wl2
67
wl3
01
wl3
23
wl3
45
wl3
67