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8-14 PXA250 and PXA210 Applications Processors Design Guide
Power and Clocking
8.5.6 Sleep Mode Timing
Sleep Mode is internally asserted, and asserts the nRESET_OUT and PWR_EN signals. The
sequence indicated in Figure 8-4 “Sleep Mode Timing” and detailed in Table 8-10, “Sleep Mode
Timing Specifications” on page 8-14 are the required timing parameters for Sleep Mode.
Table 8-9. GPIO Reset Timing Specifications
Symbol Description Min Typical Max
t
A_GP[1]
Minimum assert time of GP[1]
1
in 3.6864 MHz input clock cycles 4 cycles — —
t
DGP_OUT_A
Delay between GP[1] Asserted and nRESET_OUT Asserted in
3.6864 MHz input clock cycles
6 cycles — 8 cycles
t
DGP_OUT
Delay between nRESET_OUT asserted and nRESET_OUT
deasserted, Run or Turbo Mode
2
5 µs — 28 µs
t
DGP_OUT_F
Delay between nRESET_OUT asserted and nRESET_OUT
deasserted, during Frequency Change Sequence
3
5 µs — 380 µs
NOTES:
1. GP[1] is not recognized as a reset source again until configured to do so in software. Software should check the state of
GP[1] before configuring it as a Reset to ensure no spurious reset is generated.
2. Time is 512*N Processor Clock Cycles plus as many as 4 cycles of the 3.6864 MHz input clock.
3. Time during the Frequency Change Sequence depends on the state of the PLL Lock Detector at the assertion of GPIO
Reset. The Lock Detector has a maximum time of 350 us plus synchronization.
Figure 8-4. Sleep Mode Timing
Table 8-10. Sleep Mode Timing Specifications (Sheet 1 of 2)
Symbol Description Min Typical Max
t
A_GP[x}
Assert Time of GPIO Wake up Source (x=[15:0]) 91.6 µs — —
t
D_PWR_F
Delay from nRESET_OUT asserted to PWR_EN deasserted 61 µs — 91.6 µs
t
D_PWR_R
Delay between GP[x] asserted to PWR_EN asserted 30.5 µs — 122.1 µs
t
DSM_VCC
Delay between PWR_EN asserted and VCC stable — — 10 ms
GP[x]
PWR_EN
VCC
nVDD_FAULT
nRESET_OUT
t
DSM_OUT
Note: nBATT_FAULT must be high or PXA250 will not exit Sleep Mode
t
A_GP[x]
t
D_PWR_R
t
D_PWR_F
t
D_FAULT
t
DSM_VCC