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PXA250 and PXA210 Applications Processors Design Guide 8-7
Power and Clocking
DQM(1:0) 2
Main Memory Bus SDRAM byte
selects
VCCN
nSDCS(3:2) 2
Main Memory Bus SDRAM chip
selects
VCCN
nSDCS(1:0) 2
Main Memory Bus SDRAM chip
selects
VCCN
SDCKE(1:0) 2
Main Memory Bus SDRAM clock
enable
VCCN
SDCLK(2) 1 Main Memory Bus SDRAM clocks VCCN
SDCLK(1:0) 2 Main Memory Bus SDRAM clocks VCCN
RD/nWR 1 CC Steering Signal VCCN
CS(0) 1 Static chip selects VCCN
GP15 1 nCS_1 Active low chip select 1 VCCN
GP18 1 RDY Ext. Bus Ready VCCN
GP19 1 DREQ[1] Ext. Bus Master Request VCCN
GP20 1 DREQ[0] Ext. Bus Master Request VCCN
GP21 1 General Purpose I/O pin VCCN
GP22 1 General Purpose I/O pin VCCN
GP33 1 nCS[5] Active low chip select 5 VCCN
GP48 1
nPOE Output Enable for Card Space VCCN
GP49 1
nPWE Write Enable for Card Space VCCN
GP50 1
nPIOR I/O Read for Card Space VCCN
GP51 1
nPIOW I/O Write for Card Space VCCN
GP52 1
nPCE[1] Card Enable for Card Space VCCN
GP53 1
nPCE[2] Card Enable for Card Space
VCCN
MMCCLK MMC CLock
GP54 1
MMCCLK MMC CLock
VCCN
pSKTSEL Socket Select for Card Space
GP55 1
nPREG Card Address bit 26 VCCN
GP56 1
nPWAIT Wait signal for Card Space VCCN
GP57 1
nIOIS16
Bus Width select for I/O Card
Space
VCCN
GP78 1 nCS[2] Active low chip select 2 VCCN
GP79 1 nCS[3] Active low chip select 3 VCCN
GP80 1 nCS[4] Active low chip select 4 VCCN
Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ (Sheet 2 of 6)
Pin
Pin
Count
Alt_fn
1-(in)
Alt_fn
2-(in)
Alt_fn
1-(out)
Alt_fn
2-(out)
Signal Description and
Comments
Power
Supply