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1-16 PXA250 and PXA210 Applications Processors Design Guide
Introduction
Table 1-5. PXA210 Applications Processor Pinout — Ballpad Number Order (Sheet 1 of 2)
Ball # Signal Ball # Signal Ball # Signal
A1 DQM[1] F1 VSSN L1 VSSN
A2 L_DD[14]/GPIO[72] F2 nSDCS[0] L2 VCCN
A3 L_DD[10]/GPIO[68] F3 nSDRAS L3 MA[12]
A4 VSSQ F4 nSDCS[1] L4 MA[13]
A5 L_DD[6]/GPIO[64] F5 VCC L5 MA[11]
A6 L_DD[2]/GPIO[60] F6 L_DD[8]/GPIO[66] L6 VSSQ
A7 L_LCLK/GPIO[75] F7 L_FCLK/GPIO[74] L7 MD[2]
A8 SPPSCLK/GPIO[23] F8 SSPRXD/GPIO[26] L8 MD[6]
A9 SPPEXTCLK/GPIO[27] F9 VCC L9 VSSN
A10 nACRESET F10 FFTXD/GPIO[39] L10 MD[11]
A11 PWM[1]/GPIO[17] F11 VCC L11 BATT_VCC
A12 VSSQ F12 VSSQ L12 GPIO[54]
A13 FFRXD/GPIO[34] F13 TESTCLK L13 GPIO[55]
A14 BTCTS/GPIO[44] F14 BOOT_SEL[0] L14 GPIO[57]
A15 IRRXD/GPIO[46] F15 TEST L15 GPIO[0]
B1 RDY/GPIO[18] G1 MA[0] M1 MA[14]
B2 VSSN G2 nOE M2 MA[15]
B3 L_DD[13]/GPIO[71] G3 nWE M3 VCCN
B4 L_DD[9]/GPIO[67] G4 VCCN M4 MA[16]
B5 VSSQ G5 VSSN M5 VCCN
B6 L_DD[3]/GPIO[61] G6 RDnWR M6 VSSN
B7 L_PCLK/GPIO[76] G7 VSS M7 MD[3]
B8 VSSQ G8 VSS M8 MD[7]
B9 BITCLK/GPIO[28] G9 VSS M9 nCS[1]/GPIO[15]
B10 SDA G10 BTRXD/GPIO[42] M10 MD[10]
B11 VSSQ G11 nTRST M11 MD[13]
B12 USB_N G12 TDI M12 GPIO[48]
B13 BTRTS/GPIO[45] G13 TCK M13 GPIO[52]
B14 IRTXD/GPIO[47] G14 TMS M14 VSSN
B15 MMDAT G15 TDO M15 GPIO[56]
C1 SDCKE[1] H1 VCCN N1 VSSN
C2 SDCKE[0] H2 VSSN N2 MA[18]
C3 VCCN H3 MA[2] N3 VSS1
C4 L_DD[12]/GPIO[70] H4 MA[1] N4 MA[22]
C5 VCCQ H5 VCC N5 MA[24]
C6 L_DD[4]/GPIO[62] H6 VSSQ N6 VCCN
C7 L_BIAS/GPIO[77] H7 VSS N7 VCC