Intel PXA250 and PXA210 Chipper User Manual


 
A-6 PXA250 and PXA210 Applications Processors Design Guide
SA-1110/Applications Processor Migration
A.2.1 Software Compatibility
Because the PXA250 applications processor uses Intel® XScale™ microarchitecture, the PXA250
applications processor has a different pipeline length relative to the SA-1110. This effects code
performance when migrating between the two devices varies because of the number of clock cycles
needed for execution. Any application that relies on specific cycle counts, or has specific timing
components, will show a difference in performance.
The PXA250 applications processor features: larger caches, Branch target buffering, and faster
multiplication, and so many applications run faster than the SA-1110 when running at the same
clock frequency.
A.2.2 Address space
The physical address mapping of gross memory regions is not compatible between the PXA250
applications processor and SA-1110. For example, on the PXA250 applications processor, Static
chip selects 4 and 5 are lower in memory than PCMCIA, on the SA-1110 they are higher in the
memory space.
Changes of this kind could be managed by the Operating System remapping virtual memory pages
to new physical addresses. This assumes that the Operating System has basic support for virtual
memory, but not if this could be managed by initialization code modifications effecting the same
change.
More significantly, memory-mapped registers may have different names, new addresses and
different functionality. This impacts all device drivers and register-level firmware, that at a
minimum, requires re-mapping register address and changing the default configuration.
A.2.3 Page Table Changes
There are differences in the virtual memory Page Table Descriptors between the SA-1110 and the
PXA250 applications processors that impact software execution speed. A new bit has been added
to differentiate ARM* compliant operation modes from some features Intel includes such as access
to the Mini-Data-Cache.
If any software attempts to explicitly control page table modifications, normally the domain of the
Operating System, then that software may need annotation to allow for the extra opportunities the
PXA250 applications processor offers.
Any SA-1110 code that explicitly uses the Mini-Data-Cache is executed correctly, but it's ability to
utilize a different cache is lost without a page table bit being changed. The impact here is
performance not functionality.
A.2.4 Configuration registers
There are numerous device configuration changes in the PXA250 applications processor. You must
now select the configuration options for clock speeds such as Turbo Mode. This requirement is not
found on the SA-1110.