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8-10 PXA250 and PXA210 Applications Processors Design Guide
Power and Clocking
GP40 1 DTR FFUART data terminal Ready VCCQ
GP41 1 RTS FFUART request to send VCCQ
GP42 1 BTRXD BTUART receive data VCCQ
GP43 1 BTTXD BTUART transmit data VCCQ
GP44 1 CTS BTUART clear to send VCCQ
GP45 1 RTS BTUART request to send VCCQ
GP46 1
ICP_RXD ICP receive data
VCCQ
RXD STD_UART receive data
GP47 1
TXD STD_UART transmit data
VCCQ
ICP_TXD ICP transmit data
GP58 1 LDD[0] LCD data pin 0 VCCQ
GP59 1 LDD[1] LCD data pin 1 VCCQ
GP60 1 LDD[2] LCD data pin 2 VCCQ
GP61 1 LDD[3] LCD data pin 3 VCCQ
GP62 1 LDD[4] LCD data pin 4 VCCQ
GP63 1 LDD[5] LCD data pin 5 VCCQ
GP64 1 LDD[6] LCD data pin 6 VCCQ
GP65 1 LDD[7] LCD data pin 7 VCCQ
GP66 1
LDD[8] LCD data pin 8
VCCQ
MBREQ Alternate Bus Master Request
GP67 1
LDD[9] LCD data pin 9
VCCQ
MMCCS0 MMC Chip Select 0
GP68 1
MMCCS1 MMC Chip Select 1
VCCQ
LDD[10] LCD data pin 10
GP69 1
MMCCLK MMC_CLK
VCCQ
LDD[11] LCD data pin 11
GP70 1
RTCCLK Real Time clock (1Hz)
VCCQ
LDD[12] LCD data pin 12
GP71 1
3.6 MHz 3.6MHz Oscillator clock
VCCQ
LDD[13] LCD data pin 13
GP72 1
32 KHz 32 KHz clock
VCCQ
LDD[14] LCD data pin 14
Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ (Sheet 5 of 6)
Pin
Pin
Count
Alt_fn
1-(in)
Alt_fn
2-(in)
Alt_fn
1-(out)
Alt_fn
2-(out)
Signal Description and
Comments
Power
Supply