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8-8 PXA250 and PXA210 Applications Processors Design Guide
Power and Clocking
MMCMD 1 MMC Command VCCQ
MMDAT 1 MMC Data VCCQ
AC_RESET_n 1 ac97 RESET VCCQ
UDC+ 1 USB client high differential signal VCCQ
UDC- 1 USB client low differential signal VCCQ
SCL 1 I2C Clock VCCQ
SDA 1 I2C Bidirectional Data VCCQ
nRESET 1 Hardware reset VCCQ
nRESET_OUT 1 Reset output VCCQ
BOOT_SEL[2:0] 3 ROM Width Select (16/32) VCCQ
PWR_EN 1 power enable VCCQ
nBATT_FAULT 1 Battery Fault VCCQ
nVDD_FAULT 1 VDD Fault VCCQ
nTRST 1 JTAG Reset VCCQ
TDI 1 JTAG Data In VCCQ
TDO 1 JTAG Data Out VCCQ
TMS 1 JTAG Mode Select VCCQ
TCK 1 JTAG Clock VCCQ
TESTCLK 1 TEST Clock VCCQ
TEST 1 TEST mode VCCQ
GP0 1 Reserved for sleep wakeup VCCQ
GP1 1 GP_RST Active low GP_reset VCCQ
GP2 1 General Purpose I/O pin VCCQ
GP3 1 General Purpose I/O pin VCCQ
GP4 1 General Purpose I/O pin VCCQ
GP5 1 General Purpose I/O pin VCCQ
GP6 1 MMCCLK MMC Clock VCCQ
GP7 1 48 MHz 48 mhz clock output VCCQ
GP8 1 MMCCS0 MMC Chip Select 0 VCCQ
GP9 1 MMCCS1 MMC Chip Select 1 VCCQ
GP10 1 RTCCLK real time clock (1Hz) VCCQ
Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ (Sheet 3 of 6)
Pin
Pin
Count
Alt_fn
1-(in)
Alt_fn
2-(in)
Alt_fn
1-(out)
Alt_fn
2-(out)
Signal Description and
Comments
Power
Supply