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PXA250 and PXA210 Applications Processors Design Guide 1-3
Introduction
• System memory interface
—100MHz SDRAM
— 4 MB to 256 MB of SDRAM memory
— Support for 16, 64, 128, or 256 Mbit DRAM technologies
— 4 Banks of SDRAM, each supporting 64 MB of memory
— Clock enable (1 CKE pin is provided to put the entire SDRAM interface into self refresh)
— Supports as many as 6 static memory devices (SRAM, Flash, or VLIO)
• PCMCIA/Compact Flash card control pins
• LCD Controller pins
• Full Function UART
• Bluetooth UART
• MMC Controller pins
• SSP Pins
• USB Client Pins
• AC’97 Controller Pins
• Standard UART Pins
• I
2
C Controller pins
• PWM pins
• 15 dedicated GPIOs pins
• Integrated JTAG support
Package features of the PXA210 applications processor are:
• Core frequencies supported – 100 MHz, 133 MHz, 200 MHzSystem memory interface
— 100 MHz SDRAM, 16-bit only
— 2 MB to 128 MB of SDRAM memory
— Support for 16, 64, 128, or 256 Mbit DRAM technologies
— 2 Banks of SDRAM, each supporting 64 MB of memory
— Supports as many as 6 static memory devices (SRAM, Flash, or VLIO)
• Clock enable (1 CKE pin is provided to put the entire SDRAM interface into self refresh)
• LCD Controller pins
• Bluetooth UART
• MMC Controller pins
• SSP Pins
• USB Client Pins
• AC97 Controller Pins
• Standard UART Pins