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AWG510 & AWG520 Service Manual
v
Figure 4–20: Trigger Signal (–5V check2) 4–51. . . . . . . . . . . . . . . . . . . . . . .
Figure 4–21: Event input and enhanced mode initial test hookup 4–52. . .
Figure 4–22: Waveform while all ground disclosure switches are open
4–53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4–23: Waveform output when the SW1 is closed 4–54. . . . . . . . . . .
Figure 4–24: Waveform output when the SW2 is closed 4–55. . . . . . . . . . .
Figure 4–25: Waveform output when the SW3 is closed 4–55. . . . . . . . . . .
Figure 4–26: Waveform output when the SW4 is closed 4–56. . . . . . . . . . .
Figure 4–27: Initial waveform output 4–57. . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4–28: DC waveform output when the SW5 is closed 4–58. . . . . . . .
Figure 4–29: 10 MHz reference initial test hookup 4–59. . . . . . . . . . . . . . .
Figure 4–30: External clock input initial test hookup 4–61. . . . . . . . . . . . .
Figure 4–31: Add operation initial test hookup 4–63. . . . . . . . . . . . . . . . . .
Figure 4–32: Marker output initial test hookup 4–65. . . . . . . . . . . . . . . . . .
Figure 4–33: Digital data output initial test hookup 4–69. . . . . . . . . . . . . .
Figure 4–34: Digital data output level initial test hookup 4–72. . . . . . . . . .
Figure 4–35: Digital data output initial test hookup 4–74. . . . . . . . . . . . . .
Figure 4–36: Clock output initial test hookup 4–76. . . . . . . . . . . . . . . . . . .
Figure 4–37: Noise output initial test hookup 4–78. . . . . . . . . . . . . . . . . . . .
Figure 5–1: Cooling the waveform generator
during adjustment procedures 5–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 5–2: Accessing the service switch 5–5. . . . . . . . . . . . . . . . . . . . . . . .
Figure 5–3: Hookup for the clock frequency adjustment 5–7. . . . . . . . . .
Figure 5–4: Adjustment location for clock frequency 5–8. . . . . . . . . . . . .
Figure 5–5: Hookup for the clock duty adjustment 5–9. . . . . . . . . . . . . . .
Figure 5–6: Adjustment location for clock duty, timing, and
linearity 5–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 5–7: Hookup for the DAC clock timing adjustment 5–12. . . . . . . .
Figure 5–8: Hookup for the DAC linearity adjustment 5–15. . . . . . . . . . . .
Figure 5–9: Hookup for the noise output adjustment 5–18. . . . . . . . . . . . .
Figure 5–10: Adjustment location for noise level 5–19. . . . . . . . . . . . . . . . .
Figure 5–11: Adjustment location for the power supply unit 5–20. . . . . . .
Figure 6–1: AWG510 and AWG520 Orientation 6–12. . . . . . . . . . . . . . . . .
Figure 6–2: External modules 6–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6–3: Outer-chassis modules 6–14. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6–4: Inner-chassis modules 6–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6–5: Knob Removal 6–18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6–6: Line Fuse and Line Cord Removal 6–19. . . . . . . . . . . . . . . . . .