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MTG100 & MTG300 MPEG Generator Service Manual
3Ć1
Theory of Operation
This section describes the basic operation of the major circuit blocks or modules
in the MPEG generator. The Diagrams section, beginning on page 9-1, includes
a block diagram and an interconnect diagram. Figure 9-1 shows the modules and
functional blocks of the MPEG generator. Figure 9-2 shows how the modules
interconnect.
A10 Main Board
The A10 Main board consists of the following seven blocks.
This block consists of two SCSI controllers, two 1 MB SRAMs, HDC_CPU
(SH-3) and the peripheral circuit, and a FIFO buffer to transfer data. Since the
SCSI controllers are connected to the Ultra Wide SCSI disks in single end, this
provides a maximum data transfer rate of 20 MW/s (40 MB/s) X 2. The data read
from the SCSI disks is transferred to the SRAM and then transferred to the
Change Packet block through the FIFO buffer. The SRAM can be accessed from
the PCI or HDC_CPU. When these disks are accessed, the HDD LED on the
front panel lights.
This block consists of the CP_CPU (SH-3) and peripheral circuit, FPGA, and
4 MB SRAM for data insertion. It executes packet operation. There are two
64X32-bit buffers in the FPGA and they can receive packets from the hard disk
controllers alternately. The content of the packets is examined by the CP_CPU,
and then the contents are changed. In addition, the 10 Hz pulse produced by the
27 MHz clock is input into the CP_CPU, it is used to insert the TDT or STT
packets.
This block consists of the CW_CPU (SH-3) and peripheral circuit, and FPGA. It
executes operation for the internal value of transport stream packets. There are
two 64X32-bit buffers in the FPGA, and they can receive packets from the hard
disk controllers alternately. The content of the packets is examined by the
CW_CPU, and then the contents are changed. In addition, the 10 Hz pulse
produced by the 27 MHz clock is input into the CW_CPU, which is used to
renew the time information of the TDT or STT.
This block forms a large FIFO buffer with the 1 MB SRAM and FPGA. It
converts the burst data to constant data and transfers it to the next circuit block.
It also multiplexes 32-bit/word data to 8-bit/word data. After data output is
Hard Disk Controller (SCSI
HDDX2)
Change Packet
Change Word
Output Buffer