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Master and Slave Clock Fields (State modes only)
The Master and Slave Clock fields are used to construct a clocking
arrangement. A clocking arrangement is the assignment of appropriate
clocks, clock edges, and clock qualifier levels which allow the analyzer to
synchronize itself on valid data.
When the Master or Slave Clock field is selected, a clock/qualifier selection
menu appears showing the available clocks and qualifiers for a clocking
arrangement. In 70-MHz State mode (HP 16554) or 100-MHz State mode
(HP 16555), there are four clocks available (J, K, L, M), and four clock
qualifiers available (Q1 through Q4). In 110-MHz State mode (HP 16555),
the four clock qualifiers are available but only one clock may be selected at a
time.
A single-card module can use any of its four clocks as a state clock for
specifying Master and Slave clocking arrangements. For a multi-card module,
only the four clocks of the Clock Master board are available for use as state
clocks. Any unassigned clocks may be used as data channels.
See Also
The "Pod Clock Field" earlier in this chapter for information on selecting
clocking arrangement types such as Master, Slave, or Demultiplex.
"To install modules" in chapter 14, "Installation."
Master Clock Field
Master Clock field
The Format Menu
Master and Slave Clock Fields (State modes only)
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