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Logic Analyzer Description
The HP 16554A, 16555A, and 16555D State/Timing Analyzer modules are
part of a new generation of general-purpose logic analyzers. They are used
with the HP 16500 Logic Analysis System mainframe, which is designed as a
standalone instrument for use by digital and microprocessor hardware and
software designers. The HP 16500 mainframe has HP-IB and RS-232-C
interfaces for hard copy printouts and control by a host computer.
Both State/Timing Analyzer modules have 64 data channels, and four
clock/data channels. As many as two additional HP 16554A, 16555A, or
16555D cards can be added to expand the module to 200 data and
4 clock/data channels.
Memory depth on the HP 16554A is 500K in all pod pair groupings, or 1M on
just one pod (timing half-channel mode). Memory depth on the HP 16555A
is 1M in all pod pair groupings, or 2M on just one pod (timing half-channel
mode). Memory depth on the HP 16555D is 2M in all pod pair groupings, or
4M on just one pod (timing half-channel mode). All available resource terms
can be assigned to either configured state or timing analyzer machine.
Measurement data is displayed as data listings or waveforms.
The 70-MHz and 110-MHz state analyzers have master, slave, and
demultiplexed clocking modes available. Measurement data can be stamped
with either state or time tags. For triggering and data storage, the state
analyzer uses 12 sequence levels with two-way branching, 10 pattern
resource terms, 2 range terms, and 2 timers/counters.
The 250-MHz and 500-MHz conventional timing analyzers have variable
width, depth, and speed selections. Sequential triggering uses 10 sequence
levels with two-way branching, 10 pattern resource terms, 2 range terms,
2 timers/counters and 2 edge/glitch terms.
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