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Chapter 2: Task Guide
To select transitional timing or store qualified
setup time is the front edge of the setup/hold window relative to the
sampling clock, and the hold time is the back edge of the setup/hold
window relative to the sampling clock.
1. Select the state (synchronous sampling) mode (see “To select the state
mode” on page 44).
2. In the Format tab, select the Setup/Hold button.
3. In the Sampling Positions dialog, select the Manual Setup/Hold option.
4. For each label, enter setup/hold values. The values are adjustable in 100 ps
increments, with a fixed window of 2.5 ns.
5. If you need to adjust bits individually:
a. Select a label containing the bit.
If a bit is used in more than one label, you will change its setup and
hold value in all labels.
b. Select the Individual bits option.
c. Enter the bit number you want to change.
d. Enter the setup/hold value.
6. Close the Sampling Positions dialog.
The Manual Setup/Hold sampling positions are saved and loaded along
with the logic analyzer configuration file.
Example
Suppose you're probing a bus in the device under test whose data valid
window is 3 ns. Suppose also that the bus clock edge occurs 1 ns into
the data valid window. To place the logic analyzer's setup/hold window
within the data valid window, you could specify a setup value of 800 ps
(and hold value of 1.7 ns).