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Chapter 2: Task Guide
To select transitional timing or store qualified
saved into one sample of logic analyzer memory.
Two additional sampling clock modes let you capture data differently:
•In the Master/Slave mode, you can save data captured on different clock
edges into the same sample of logic analyzer memory.
When the slave clock occurs, data captured on the pods that use the slave
clock is saved in a slave latch. Then, when the master clock occurs, data
captured on the pods that use the master clock, as well as the slave latch
data, are saved into logic analyzer memory.
•In the Demultiplex mode, you can demultiplex data being probed by one
pod into the logic analyzer memory that is normally used for two pods.
When the slave clock occurs, data captured on the pod is saved into the
slave latch for the other pod in the pod pair. Then, when the master clock
occurs, data captured on the pod, as well as the slave latch data, are saved
in logic analyzer memory.
To set up the master sampling clock mode
1. In the Sampling tab, with State Mode selected, select the Master only
mode in the Clock Setup area.