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Chapter 3: Reference
The Sampling Tab
under test) that will enable (qualify) the sampling clock.
Generally, the state mode sampling clock is taken from the
signals that clock valid data in the device under test.
The clock channel specifiers graphically show your clock
setup. Edges are ORed ("+") together, and qualifiers are
ANDed (".") to all edges. To qualify just one of the edges,
switch to Advanced Clocking.
All clock channels for the clock setup must be on the pods
of the master card of the module, but the pods do not
need to be part of the state measurement.
Advanced
Clocking Lets you specify more complex clock setups than you can
with the normal Master (and perhaps Slave) buttons that
are available for each pod.
See Also “Selecting the State Mode (Synchronous Sampling)” on page 43
“In Either Timing Mode or State Mode” on page 52