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P/O RF Deck
Detector 0
Sample/Hold
Detector 1
ALC
Control
Modulator Control
Internal AM
(From A8 PCB)
D0 - D15
L_SEL3
A01 - A03
From
CPU
Pulse
Level Amp
Serial Data
(From
A16 PCB)
Detector 1
2 - 20 GHz
YIG
Oscillator
To Step
Attenuator
or
RF Output
Detector 0
P/O A9 PCB
P/O A6 PCB
ALC
Modulator
Driver
Serial/
Parallel
Converter
Log
Amp
Sample/Hold
Control
Address /
Data
Latches
Shaper/
Amp
Shaper
DAC
0.01 - 2 GHz
Down
Converter
Level
Detector
Switched
Filter
P/O A10 PCB
Non-Pulse
Level Amp
AM
INPUT
SENS
DAC
EPLD
Detector
CAL
DAC
Level
REF
DAC
ALC
Gain
CAL
DAC
Switch
Control
Circuits
0.01 - 20 GHz
0.01 -
40 GHz
Forward
Coupler
External AM
(From Front /
Rear Panel)
ALC Slope
(From A12 PCB)
LOG AMP
AM
CAL
DAC
SLOPE
DAC
Detector
MUX
External ALC
(From Front /
Rear Panel)
D0 - D15
L. SEL 2
A01 - A02
(From CPU)
10 MHz
(From A5 PCB)
Pulse
Generator
External Pulse Inputs
(From Front / Rear Panel)
Pulse
Pulse
Sample / Hold
Shaper/
Amp
Driver/
Amp
P/O A14 PCB
Buffer
Amp
Source
Quadrupler
Module
0.01 -
65 GHz
Switched
Doubler
Module
40 -
65 GHz
10 - 16.25 GHz
Modulator Control
Fixed
Gain
FUNCTIONAL ALC/AM/PULSE
DESCRIPTION MODULATION
682XXB/683XXB 2-17
Figure 2-3. Block Diagram of the ALC/AM/Pulse
Modulation Subsystem