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available) bit in the Status Byte register is set. This
varies slightly from the 488.2 standard in that the
MAV bit will only be set when at least one com-
plete response message is present in the output queue.
A complete response message consists of response
message text and a message terminator (NL).
Buffer Deadlock
Buffer deadlock is occurs when the 801G* tries to
put a response message in the output queue, the
output queue is full, and the controller is held off
while sending a new message because the input buffer
is full. If deadlock occurs, the 801G* will clear its
output queue, set the query error (QYE) bit in the
Event Status register and proceed to parse incom-
ing messages. If any additional queries are requested
while in deadlock, those response messages will be
discarded.
The 801G* will clear the buffer deadlock when it
finishes parsing the current command/query. The
QYE bit will remain set until read with the *ESR?
query or cleared with the *CLS common command.
The Status Byte
The Status Byte used by the 801G* is the same as
that defined by the IEEE-488.2 standard and does
not use any other bits of the Status Byte. The Status
Byte is one part of a complete status reporting sys-
tem shown on the next set of facing pages. The Sta-
tus Byte is read by using the serial poll feature of
your controller.
Requesting Service
The GPIB provides a method for any device to in-
terrupt the controller-in-charge and request servic-
ing of a condition. This service request function is
handled with the Status Byte. When the RQS bit of
the Status Byte is true, the 801G* is requesting ser-
vice from the controller. There are many conditions