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9-3
AWG510 & AWG520 Service Manual
Clock
A40
TCXO
DDS
PLL OSC
Clock Divider
A50
SEQ circuit
SEQ memory
A60
Waveform Memory
Shift Register
AWG
Back
Plane
GPIB Board
Ethernet LAN Interface
CPU
Flash disk
3GB
hard disk
Fan
LAN Connector
A10/A11
Connector
GPIB Connector
A20 Front Panel
Bezel Switch
A90 Key Board
A75
Noise
Generator
CH1
1GHz DAC
CH1
1GHz DAC
Filter AMP Attenuator
Calibration Offset
Analog Output
A70
Analog Signal
Bus Clock
Shift Register
Fan Control
Power Supply
SIMM 64MB
FDD
MISC
VGA
COM1
ISA
Bus
Control Signal
(Op.03, AWG520)
Fan
Control
+5 V, +12 V
+5 V, -4.6 V, +12 V, +24 V
+5 V
-4.6 V
-2 V
+8 V
-8 V
+12 V
A60
Waveform Memory
FDD
!0 MHz Reference Clock
Trigger
Marker Output
Digital Data Out (Option 3)
Clock Output
Event Input
CH1
CH2 (AWG520)
/CH1 (AWG510)
CPU unit
A30
External Clock (from J320101)
Figure 9-1: Block diagram