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Chapter 3: Testing Performance
To test the multiple-clock state acquisition
Connect and configure the logic analyzer
1 Using the 6-by-2 test connectors, connect the first combination of logic
analyzer clock and data channels listed in one of the following tables to the
pulse generator.
If you are testing a 1680/81/90/91A,AD, you will repeat this test for the second
combination.
2 Using SMA cables, connect channel 1, channel 2, and trigger of the
oscilloscope to the pulse generator.
Connect the 1680/81/90/91A,AD Logic Analyzer to the Pulse Generator
Testing
Combinations
Connect to 8133A
Channel 2 Output
Connect to 8133A
Channel 2 Output
Connect to 8133A
Channel 1 Output
1 Pod 1, channel 3
Pod 3, channel 3
Pod 5, channel 3
Pod 7, channel 3
Pod 2, channel 3
Pod 4, channel 3
Pod 6, channel 3
Pod 8, channel 3 *
Clock/data channel for
Pod 1, 2, 3, and 4
(Clk 1, Clk 2, Clk 3,
Clk 4)
2 Pod 1, channel 11
Pod 3, channel 11
Pod 5, channel 11
Pod 7, channel 11
Pod 2, channel 11
Pod 4, channel 11
Pod 6, channel 11
Pod 8, channel 11 *
Clock/data channel for
Pod 1, 2, 3, and 4
(Clk 1, Clk 2, Clk 3,
Clk 4)
*1680A, AD or 1690A, AD only.