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Chapter 3: Testing Performance
To test the single-clock, single-edge, state acquisition
To test the single-clock, single-edge, state acquisition
Testing the single-clock, single-edge, state acquisition verifies the performance of
the following specifications:
• Minimum master-to-master clock time.
• Maximum state acquisition speed.
• Setup/Hold time for single-clock, single-edge, state acquisition.
This test checks two combinations of data channels using a single-edge clock at
two selected setup/hold times.
Equipment Required
Set up the equipment
If you have not already done so, do the following procedures:
“To set up the test equipment and the logic analyzer” on page 23.
“To set up the logic analyzer for the state mode tests” on page 33.
Connect and configure the logic analyzer
1 Using the 6-by-2 test connectors, connect the first combination of logic
analyzer clock and data channels listed in one of the following tables to the
pulse generator.
If you are testing a 1680/81/90/91A,AD, you will repeat this test for the second
combination.
Equipment Critical Specifications Recommended Model/Part
Pulse Generator 200 MHz 2.5 ns pulse width, <600 ps rise time 8133A option 003
Digitizing Oscilloscope ≥6 GHz bandwidth, <58 ps rise time 54750A w/ 54751A
Adapter SMA(m)-BNC(f) 1250-1200
SMA Coax Cable (Qty 3) 18 GHz bandwidth 8120-4948
Coupler BNC(m)(m) 1250-0216
BNC Test Connector,
6x2 (Qty 4)