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Status and Events
4-10 AFG3000 Series Arbitrary/Function Generators Reference Manual
Questionable Enable Register (QENR). The QENR consists of bits defined exactly
the same as bits 0 through 15 in the QEVR register (see Figure 4-9). You can use
this register to control whether the QSB in the SBR is set when an event occurs and
the corresponding QEVR bit is set.
Use the STATus:QUEStionable:ENABle command to set the bits in the OENR.
Use the STATus:QUEStionable:ENABle? query to read the contents of the OENR.
Figure 4-9: Questionable Enable Register (QENR)
Queues
There are two types of queues in the status reporting system: output queue and
error/event queues.
Output Queue
The output queue is an FIFO (first-in, first-out) queue that holds response messages
to queries awaiting retrieval. When there are messages in the queue, the MAV bit
in the SBR is set.
The output queue is emptied each time a command or query is received, so the
controller must read the output queue before the next command or query is issued.
If this is not done, an error occurs and the output queue is emptied; however, the
operation proceeds even if an error occurs.
Error/Event Queue
The event queue is an FIFO queue, which stores events as they occur in the instru-
ment. If more than 64 events are stored, the 64th event is replaced with event code
–350 (“Queue Overflow”).
The oldest error code and text are retrieved by using one of the following queries:
SYSTem:ERRor[:NEXT]?
First, issue the *ESR? query to read the contents of the SESR. The contents of the
SESR are cleared after they are read. If an SESR bit is set, events are stacked in the
Error/Event Queue. Retrieve the event code with the following command
sequence:
*ESR?
SYSTem:ERRor[:NEXT]?
If you omit the *ESR? query, the SESR bit will remain set, even if the event disap-
pears from the Error/Event Queue.
FREQ
FREQ
76543210
7 6 5 4 3 2 1 0
98
9 8
15
15
10
10
12
12
13
13
14
14
11
11