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STATUS BYTE
3-32
Standard event registers
This register is defined by IEEE 488.2 and each bit has the meaning shown below:-
*ESR?
*ESE
*ESE?
Register
Read/Write
Commands
<esb>
&
&
&
&
&
&
&
&
<pon>
<pon>
<pon>
d
e
<dde>
<dde>
<dde>
d
e
<cme>
<cme>
<cme>
d
e
<rqc>
<rqc>
<rqc>
d
e
<urq>
<urq>
<urq>
d
e
<qye>
<qye>
<qye>
d
e
<exe>
<exe>
<exe>
d
e
<opc>
<opc>
<opc>
d
e
7
7
35
5
1
1
6
6
2
2
4
43
0
0
Transition
Filter #
Condition
Register
Status
Register
C0069
# Positive transition sets status.
Enable
Register
OR
<pon> power on
<urq> user request - not implemented in this product
<cme> command error
<exe> execution error
<dde> device dependent error
<qye> query error
<rqc> request control - not implemented in this product
<opc> operation complete - set in response to the *OPC command for
synchronization.
<esb> standard event register summary bit