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SECTION 6 GPIB
6-22
Definition of bits in status byte register
DB2 QUE (Error/Event QUEue) Indicates that the error/event queue is not empty.
DB3 QUES (QUEStionable status Summary bit of questionable status register
register summary)
DB4 MAV (Message Available) The response buffer contains data.
DB5 ESB (Event Summary Bit) Summary bit of standard event status register
DB6 RQS (ReQuest Service) RQS message
MSS (Master Summary Status) Indicates that at least one service request cause is in the
device.
DB7 OPER (OPERation status Summary bit of operation status register
register summary)
Definition of bits in standard event status register
DB0 OPC (OPeration Complete) Indicates all the specified operation is completed.
DB2 QYE (QuerY Error) Indicates that a query error occurred.
DB3 DDE (Device Dependent Error) Indicates a device error occurred.
DB4 EXE (EXecution Error) An execution error occurred.
DB5 CME (CoMmand Error) A command error occurred.
DB6 URQ (User ReQuest) User-defined bit
DB7 PON (Power ON) Indicates that the power was turned on.
6.5.3 SCPI standard status register
The SCPI standard contains the following registers in addition to the register configuration defined in the 488.2
standard.
OPERation register Reports a part of the device state.
QUEStionable register Reports the signal state.
OPERation register Bit 0: Frequency Sweeping
1: Level Sweeping
2: Memory Sweeping
QUEStionable register Bit 0: AM uncal
1: FM uncal
2: Level uncal
3: RF amplifier abnormal
4: Synthesizer unlock
5: Reference signal abnormal
6: RF out shut-down by RPP
15 0
15 0