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42
Chapter 2: Task Guide
To select transitional timing or store qualified
NOTE: When the Sample Period is 1.25 ns, data is acquired at four times the trigger
sequencer rate. This, along with other half-channel mode characteristics,
means that data must be present for at least five samples before the trigger
sequencer can reliably detect it. The trigger sequencer cannot detect data
present for less than two sample periods, and could miss data present for less
than five sample periods.
The trigger sequencer treats the data as a group of four samples for each
sequencer clock. This means that the trigger point indication could be off by
up to three samples.
Although the trigger sequencer cannot detect all data, the analyzer will
correctly capture all data present for at least one sample period.
2. If you chose the 800 MHz Half Channel 8M Sample configuration, select
the Format tab and choose which pod of the pod pair will be used to
sample data.
See Also “To specify the sample period” on page 42
To specify the sample period
When the logic analyzer is in timing (asynchronous sampling) mode,
the Sample Period setting specifies how often the logic analyzer
samples the signals from the device under test.
1. In the Sampling tab, with Timing Mode selected, enter the desired time
between logic analyzer samples.
To capture signal level changes reliably, the sample period should be less
than half (many engineers prefer one-fourth) of the period of the fastest
signal you want to measure.
The sample rate is the inverse of the sample period.
NOTE: In conventional timing mode the sample rate is fixed at 1.25 ns.