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Chapter 31 External Bus
2.External Bus Interface Registers
For all the areas connected to SDRAM/FCRAM, set these bits to the same RAS - CAS delay cycle.
[Bit 11] W11: Reserved bit
Be sure to set this bit to 0.
[Bits 10 - 8] W10 to W08 (CAS latency Cycle): CAS latency
Set these bits to the CAS latency.
Table 4.2 - 20 lists the settings for the CAS latency.
For all the areas connected to SDRAM/FCRAM, set these bits to the same CAS latency.
[Bits 7 - 6] W07 and W06 (Read - >Write Cycle): Read - to - write cycle
Set these bits to the minimum number of cycles from the last read data input cycle to the write command
issuance. Set the minimum number of cycles taken until issuance.
Table 4.2 - 21 lists the settings for the read - to - write cycle.
For all the areas connected to SDRAM/FCRAM, set these bits to the same read - to - write cycle.
The number of read - to - write idle cycles is one smaller than the number of cycles set by this bit.
[Bits 5 - 4] W05 and W04 (Write Recovery Cycle): Write recovery cycle
Set these bits to the minimum number of cycles from the last write data output to the next read command
issuance.
1 1 1 8 cycles
Table 2-11 CAS Latency Setting
W10 W09 W08 CAS latency
0 0 0 1 cycle
0 0 0 2 cycles
... ...
1 1 1 8 cycles
Table 2-12 Read - to - write cycle
W07 W06 Read - to - write cycle
0 0 1 cycle
0 1 2 cycles
1 0 3 cycles
1 1 4 cycles
Table 2-10 Setting the Number of Cycles from RAS Output to CAS Output
W14 W13 W12 RAS-CAS delay cycle
