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Chapter 14 PLL Interface
5.Recommended Settings
5. Recommended Settings
• Important remark: Not all settings which are shown in this table are available for all devices. Please consult
the available datasheet for each device for the maximum allowed PLL output and the allowed maximum
frequencies for each clock domain (CLKB, CLKP and CLKT) respectively.
PLL Input
(CK)
[MHz]
Frequency Parameter Clockgear Parameter PLL Output
(X)
[MHz]
Core base
Clock
[MHz]
DIVM DIVN DIVG MULG
4 2 25 16 24 200 100
4 2 24 16 24 192 96
4 2 23 16 24 184 92
4 2 22 16 24 176 88
4 2 21 16 20 168 84
4 2 20 16 20 160 80
4 2 19 16 20 152 76
4 2 18 16 20 144 72
4 2 17 16 16 136 68
4 2 16 16 16 128 64
4 2 15 16 16 120 60
4 2 14 16 16 112 56
4 2 13 16 12 104 52
4 2 12 16 12 96 48
4 2 11 16 12 88 44
4 4 10 16 24 160 40
4 4 9 16 24 144 36
4 4 8 16 24 128 32
4 4 7 16 24 112 28
4 6 6 16 24 144 24
4 8 5 16 28 160 20
4 10 4 16 32 160 16
4 12 3 16 32 144 12