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HD151TS207SS
Rev.1.00, Apr.25.2003, page 17 of 38
I
2
C Controlled Register Bit Map (cont.)
Byte16 Control Register
Bit Description Contents Type Default Note
3V66 divider ratio =
7 3V66 / PCI / PCIF Divider Control
Bit3
R/W X
6 3V66 / PCI / PCIF Divider Control
Bit2
0010 = 1/2,
0011 = 1/3,
0100 = 1/4,
0101 = 1/5,
0110 = 1/6,
0111 = 1/7
1000 = 1/8
1001 = 1/9
1010 = 1/10
1011 = 1/11
R/W X
5 3V66 / PCI / PCIF Divider Control
Bit1
R/W X
4 3V66 / PCI / PCIF Divider Control
Bit0
PCI / PCIF divider ratio = 3v66 x
1/2
R/W X
3 SRC Divider Control Bit3 R/W X
2 SRC Divider Control Bit2 R/W X
1 SRC Divider Control Bit1 R/W X
0 SRC Divider Control Bit0
0001 = 1/1,
0010 = 1/2,
0011 = 1/3,
0100 = 1/4,
0101 = 1/5,
0110 = 1/6
0111 = 1/7
1000 = 1/8
1001 = 1/9
1010 = 1/10
1011 = 1/11
R/W X
Byte17 Control Register
Bit Description Contents Type Default Note
7 Reserved R/W 0
6 Reserved R/W 0
5 Reserved R/W 0
4 PLL2 Output (VCO2) Frequency
Control Bit
(M2 / N2 Divider Control Bit)
PLL2 : for CPU
0 = Normal mode
VCO2 frequency is changed on
Table 5 selection decided by
FS4/3/2/A/B or B9[5:1].
1 = Over or Down clocking mode
VCO2 frequency is changed by
B17[3:0] and B18[7:0] with
decimal.
B17[3:0] and B18[7:0] are able to
be changed at B17[4] = 1.
R/W 0
3 VCO2 Frequency Control Bit11 R/W 0
2 VCO2 Frequency Control Bit10 R/W 1
1 VCO2 Frequency Control Bit9 R/W 0
0 VCO2 Frequency Control Bit8
These bits are 100MHz digit of
VCO2 frequency.
0000 = 0, 0001 = 1 …. 1001 = 9
R/W 0
See
Note
1
Note: 1. B17[3:0] and B18[7:0] must be written together (at writing B18) in every case.