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4.0 Electrical & Mechanical Specifications
4.5 Channel Unit Interface Timing
Bt8960
Single-Chip 2B1Q Transceiver
N8960DSB
4.5 Channel Unit Interface Timing
Table 4-7. Channel Unit Interface Timing Requirements, Parallel Master Mode
Symbol Parameter Minimum Maximum Units
14 TQ[1,0] Setup prior to QCLK Falling Edge 100 ns
15 TQ[1,0] Hold after QCLK Low 25 ns
Table 4-8. Channel Unit Interface Switching Characteristics, Parallel Master Mode
Symbol Parameter Minimum Maximum Units
16 RQ[1,0] Hold after QCLK Rising Edge –50 ns
17 RQ[1,0] Delay after QCLK High 50 ns
Figure 4-3. Channel Unit Interface Timing, Parallel Master Mode
14
15
16
17
RQ[1,0]
QCLK
TQ[1,0]
