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1.0 System Overview
1.3 Pin Descriptions
Bt8960
Single-Chip 2B1Q Transceiver
N8960DSB
Test and Diagnostic Interface
TDI JTAG Test Data
Input
I JTAG test data input per IEEE Std 1149.1-1990. Used for loading all serial
instructions and data into internal test logic. Sampled on the rising edge of TCK.
TDI can be left unconnected if it is not being used because it is pulled-up inter-
nally.
TMS JTAG Test Mode
Select
I JTAG test mode select input per IEEE Std 1149.1-1990. Internally pulled-up
input signal used to control the test-logic state machine. Sampled on the rising
edge of TCK. TMS can be left unconnected if it is not being used because it is
pulled-up internally.
TDO JTAG Test Data
Output
O JTAG test data output per IEEE Std 1149.1-1990. Three-state output used for
reading all serial configuration and test data from internal test logic. Updated on
the falling edge of TCK.
TCK JTAG Test Clock
Input
I JTAG test clock input per IEEE Std 1149.1-1990. Used for all test interface and
internal test logic operations. If unused, TCK should be pulled low.
SMON Serial Monitor O Serial data output used for real-time monitoring of internal signal-path registers.
The source register is selected through the Serial Monitor Source Select Regis-
ter [serial_monitor_source; 0x01]. 16-bit words are shifted out, LSB first, at 16
times the symbol rate. The rising edge of QCLK defines the start Least Signifi-
cant Bit (LSB) of each word. The output is updated on the rising edge of an inter-
nal clock running at 16 times QCLK.
DTEST[1:4] Digital Tests 1–4 I Active-high test inputs used by Rockwell to enable internal test modes. These
inputs should be tied to digital ground (DGND).
DTEST[5, 6] Digital Test 5, 6 I Active-low test inputs used by Rockwell to enable internal test modes. These
inputs should be tied to the I/O buffer power supply (VDD2).
ATEST[1,2] Analog Test 1, 2 IA Analog test inputs used by Rockwell for internal test modes. These inputs
should be left floating (No Connect, NC).
Power and Ground
VDD1 Core Logic Power
Supply
– Dedicated supply pins powering the digital core logic functions.
VDD2 I/O Buffer Power
Supply
– Dedicated supply pins powering the digital I/O buffers.
DGND Digital Ground – Dedicated ground pins for the digital circuitry. Must be held at same potential as
AGND.
VAA Analog Power
Supply
– Dedicated supply pins powering the analog circuitry.
AGND Analog Ground – Dedicated ground pins for the analog circuitry. Must be held at the same poten-
tial as DGND.
Table 1-2. Hardware Signal Definitions (4 of 4)
Pin Label Signal Name I/O Definition
