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3.0 Registers
3.1 Conventions
Bt8960
Single-Chip 2B1Q Transceiver
N8960DSB
3.2.63 0x77—Scratch Pad Write Tap Select (sp_tap_select_write)
A 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 63 decimals.
When written, it causes the lowest-order 8 bits of the Access Data Register [access_data_byte[3:0]; 0x7C–
0x7F] to be subsequently written to the selected scratch pad memory location within two symbol periods. Does
not affect the value of the access data register.
3.2.64 0x78—Equalizer Read Select Register (eq_add_read)
A 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 47 decimals.
When written, it causes the selected 16-bit location of the equalizer register file to be subsequently loaded into
the lowest-order bits of the Access Data Register [access_data_byte[3:0]; 0x7C–0x7F] within two symbol peri-
ods. Does not affect the value of the register file location. An address map of the shared register file, as defined
by the factory-delivered microcode, is shown below.
7 6 5 4 3 2 1 0
– – D[5] D[4] D[3] D[2] D[1] D[0]
7 6 5 4 3 2 1 0
– – D[5] D[4] D[3] D[2] D[1] D[0]
D[5:0]
Stored Parameter
Decimal Binary
0–7 00 0000–00 0111 FFE Coefficients 0–7
8–15 00 1000–00 1111 FFE Data Taps 0–7
16–20 01 0000–01 0100 EP Coefficients 0–4
21–25 01 0101–01 1001 EP Data Taps 0–4
26 01 1010 DAGC Gain - Least-Significant Word
27 01 1011 DAGC Gain - Most-Significant Word
28 01 1100 DAGC Output
29 01 1101 FFE Output
30 01 1110 DAGC Input
31 01 1111 FFE Output, Delayed 1 Symbol Period
32 10 0000 DAGC Error Signal
33 10 0001 Equalizer Error Signal
34 10 0010 Slicer Error Signal
35–47 10 0011–10 1111 Reserved
