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3.0 Registers
3.1 Conventions
Bt8960
Single-Chip 2B1Q Transceiver
N8960DSB
3.2.4 0x03—Interrupt Mask Register High (mask_high_reg)
Independent read/write mask bits for each of the IRQ Source Register [irq_source; 0x05] interrupt flags. Indi-
vidual mask bit behavior is identical to that specified for Interrupt Mask Register Low [mask_low_reg; 0x02].
sync Sync Indication
high_felm Far-End Level Meter High Alarm
low_felm Far-End Level Meter High Alarm
low_snr Signal-to-Noise Ratio Low Alarm
3.2.5 0x04—Timer Source Register (timer_source)
Independent read/write (zero only) interrupt flags, one for each of eight internal timers. Each flag bit is set and
stays set when its corresponding timer value transitions from one to zero. If unmasked, this event will cause the
IRQ
output to be activated. Flags are cleared by writing them with a logic zero value. Once cleared, a steady-
state timer value of zero will not cause a flag to be reasserted. Clearing an unmasked flag will cause the IRQ
output to return to the inactive state, if no other unmasked interrupt flags are set.
t4 General Purpose Timer 4
t3 General Purpose Timer 3
snr SNR Alarm Timer
meter Meter Timer
sut4 Startup Timer 4
sut3 Startup Timer 3
sut2 Startup Timer 2
sut1 Startup Timer 1
7 6 5 4 3 2 1 0
– – – – sync high_felm low_felm low_snr
7 6 5 4 3 2 1 0
t4 t3 snr meter sut4 sut3 sut2 sut1
