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2.0 Functional Description
2.2 Receive Section
Bt8960
Single-Chip 2B1Q Transceiver
N8960DSB
2.2.2 Analog-to-Digital Converter
The ADC provides 16 bits of resolution. The analog input from the variable gain
amplifier is converted into digital data and output at the symbol rate.
2.2.3 Digital Signal Processor
The Digital Signal Processor (DSP) includes five Least Mean Squared (LMS) fil-
ters: an Echo Canceller (EC), a Digital Automatic Gain Controller (DAGC), a
Feed Forward Equalizer (FFE), an Error Predictor (EP), and a Decision Feedback
Equalizer (DFE). These filters are used to equalize the received signal so that the
symbols transmitted from the far-end can be reliably recovered. The DSP uses
symbol rate sampling for all processing functions. Their interconnections and
relationships to the digital front-end and the detector are illustrated in Figure 2-3.
Figure 2-3. Receiver Digital Signal Processing
Digital
Front-End
Channel
Unit
Interface
Echo Canceller
Transmit
Symbol
Equalizer
DFE
Detector
LEC
DAGC
FFE
NEC
EP
PKD
Slicer
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