Registers
Register Summary
Bt8960
Single-Chip 2B1Q Transceiver
41
N8960DSB
0x38 dagc_target_low R/W D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
0x39 dagc_target_high R/W D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8]
0x3A detector_modes R/W
enable_peak_
detector
output_mux_
control[1]
output_mux_
control[0]
scr_out_to_dfe two_level lfsr_lock htur_lfsr descr_on
0x3B peak_detector_delay R/W — — — — D[3] D[2] D[1] D[0]
0x3C dagc_modes R/W — — — — —
eq_error_
adaption
adapt_
coefficient
adapt_gain
0x3D ffe_modes R/W — — — — adapt_last_coeff
zero_
coefficients
adapt_
coefficient
adapt_gain
0x3E ep_modes R/W — — — — zero_output
zero_
coefficients
adapt_
coefficients
adapt_gain
0x40 pdm_low R/W D[17] D[16] D[15] D[14] D[13] D[12] D[11] D[10]
0x41 pdm_high R/W D[25] D[24] D[23] D[22] D[21] D[20] D[19] D[18]
0x42 overflow_meter R/W D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
0x44 dc_meter_low R/W D[23] D[22] D[21] D[20] D[19] D[18] D[17] D[16]
0x45 dc_meter_high R/W D[31] D[30] D[29] D[28] D[27] D[26] D[25] D[24]
0x46 slm_low R/W D[23] D[22] D[21] D[20] D[19] D[18] D[17] D[16]
0x47 slm_high R/W D[31] D[30] D[29] D[28] D[27] D[26] D[25] D[24]
0x48 felm_low R/W D[23] D[22] D[21] D[20] D[19] D[18] D[17] D[16]
0x49 felm_high R/W D[31] D[30] D[29] D[28] D[27] D[26] D[25] D[24]
0x4A noise_histogram_low R/W D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
0x4B noise_histogram_high R/W D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8]
Table 3-1. Register Table (4 of 6)
ADDR
(hex)
Register
Label
Read
Write
Bit Number
7 6 5 4 3 2 1 0
