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Appendix D: Performance Verification
73A-270 Arbitrary Pulse/Pattern Generator Module
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Table A–6: (Cont.)VXIbus TTL Trigger Line Verification Ch. A triggered by Ch. B
TTLTRG Line Change Setup, Restart Pattern, Verify 500 kHz Pulse-Pattern
TTLTRG6* IBWRT "Q68X86T"
IBWRT "1B"
TTLTRG7* IBWRT "Q78X87T"
IBWRT "1B"
4. Using the following commands, disable both channels from the TTLTRGX*
lines and then resend the trigger pulse from channel B to restart the
pulse-pattern from channel A. Check that channel A is not putting out a
pulse pattern, and then stop the pulse-pattern:
IBWRT "Q88X88T"
IBWRT "1B"
(Verify no pulse-pattern from channel A)
IBWRT "Q"
5. Verify the EXT TRG A input with the following steps:
a. Connect TTL OUT B to EXT TRG A.
b. Restart both channels with the following command:
IBWRT "1B"
c. Verify a 500 kHz pulse pattern from channel A (triggered by channel B)
and then stop the pattern.
IBWRT "Q"
(Verify that the pattern stopped)
d. Disconnect TTL OUT B from EXT TRG A.
6. Verify channel A breakpoint recognition with the following steps:
a. Set the 73A-270 to generate a continuous pulse pattern having a 10 ms
active high level pulse with an active breakpoint followed by a 10 ms
active low level pulse with an active breakpoint with the following
commands:
IBWRT "0S3R0A0M1003L1006L0C"
b. Trigger the pulse-pattern and check that the TTL OUT A pulse-pattern is
held at a TTL high level, confirming that the pattern stopped at the
active high pulse breakpoint.