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Agilent N518xA, E8663B, E44x8C, and E82x7D Signal Generators Programming Guide 181
Programming the Status Register System
Status Groups
Data Questionable BERT Condition Register
The Data Questionable BERT Condition Register continuously monitors the hardware and firmware
status of the signal generator. Condition registers are read only.
Table 4-12 Data Questionable BERT Condition Register Bits
Bit Description
0 No Clock. A 1 in this bit position indicates no clock input for more than 3 seconds.
1 No Data Change. A 1 in this bit position indicates no data change occurred during the last 200 clock signals.
2 PRBS Sync Loss. A 1 is set while PRBS synchronization is not established. *RST sets the bit to zero.
3−10 Unused. These bits are always set to 0.
11 Down conv. / Demod Unlocked. A 1 in this bit position indicates that either the demodulator or the down converter
is out of lock.
12 Demod DSP Ampl out of range. A 1 in this bit position indicates the demodulator amplitude is out of range. The
*RST command sets this bit to zero (0).
13 Sync. to BCH/TCH/PDCH. If the synchronization source is BCH, a 1 in this bit position indicates BCH
synchronization is not established; it does not indicate the TCH/PDCH synchronization status. If the sync source is
TCH or PDCH, a 1 in this bit position indicates that TCH or PDCH synchronization is not established.
*RST sets this
bit to zero.
14 Waiting for TCH/PDCH. A 1 in this bit position indicates that a TCH or PDCH midamble has not been received. This
bit is set when bit 13 is set. The bit is also set when the TCH or PDCH synchronization was once locked and then
lost (in this case the front panel displays “WAITING FOR TCH (or PDCH)”).
*RST sets this bit to zero.
15 Always 0.
Query: STATus:QUEStionable:BERT:CONDition?
Response: The decimal sum of the bits set to 1.