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Specifications
The specifications are the performance standards against which the product
is tested.
HP 16554A, 16555A, and 16555D
Minimum State Clock Pulse Width
1
3.5 ns
Threshold Accuracy
±
(100 mV + 3% of threshold setting)
Setup/Hold Time:
1
Single Clock, Single Edge 0.0/3.5 ns through 3.5/0.0 ns,
adjustable in 500-ps increments
Single Clock, Multiple Edges: 0.0/4.0 ns through 4.0/0.0 ns,
adjustable in 500-ps increments
Multiple Clocks, Multiple Edges: 0.0/4.5 ns through 4.5/0.0 ns,
adjustable in 500-ps increments
HP 16554A only
The HP 16554A requires operating system v3.00 or later to operate.
Maximum State Speed 70 MHz
Minimum Master-to-Master Clock Time
1
14.285 ns
HP 16555A/D only
Clock Scheme:
Single Clock, Single Edge:
Maximum State Speed 110 MHz
2
Minimum Master-to-Master Clock Time
1
9.09 ns
2
Single Clock or Multiple Clock, Multiple Edges:
Maximum State Speed 100 MHz
Minimum Master-to-Master Clock Time
1
10.0 ns
1
Specified for an input signal VH =
−
0.9 V, VL =
−
1.7 V, and threshold =
−
1.3 V.
2
An HP 16555A in an HP 16500B mainframe using operating system v2.xx has maximum state speed of 100 MHz and minimum
Master-to-Master Clock Time of 10.0 ns for single-clock, single-edge clocking. 110-MHz single-clock state acquisition mode is
available with HP 16500B mainframe operating system v3.00 or higher or HP 16500C mainframe operating system v1.00 or higher
(refer to "Operating System"). The maximum state acquisition speed is 100 MHz for all other clocking modes.
Specifications and Characteristics
Specifications
13–3