Key Features for the HP 16555D
•
110-MHz state and 500-MHz timing acquisition speed.
•
64 data channels/4 clocks expandable to 200 data/4 clock channels.
•
Lightweight passive probes for easy hookup and compatibility with
previous HP logic analyzers and preprocessors.
•
HP-IB and RS-232-C interface for programming and hard copy printouts.
•
Variable setup/hold time, 3.5-ns window.
•
External arming to and from other modules through the intermodule bus.
•
2-M deep memory on all channels with 4 Mbytes in half-channel modes.
•
Marker measurements.
•
12 levels of trigger sequencing for state and 10 levels of sequential
triggering for Timing.
•
Both state and timing analyzers can use 10 pattern resource terms, two
range terms, and two timer/counters to qualify and trigger on data. The
timing analyzer also has two edge terms available.
•
Time (8-ns resolution) and number-of-qualified-states tagging.
•
Full programmability.
•
Mixed State/Timing and State/State (interleaved) display.
•
Waveform display.
General Information
Key Features for the HP 16555D
1–7