TSR
Timer Status Register
Register Summary 10-51
TSR
SPR 0x3D8 Read/Clear
See “Timer Status Register (TSR)” on page 6-8.
Figure 10-34. Timer Status Register (TSR)
0 ENW Enable Next Watchdog
0 Action on next watchdog event is to set
TSR[ENW] = 1.
1 Action on next watchdog event is
governed by TSR[WIS].
Software must reset TSR[ENW] = 0 after
each watchdog timer event.
1 WIS Watchdog Interrupt Status
0 No Watchdog interrupt is pending.
1 Watchdog interrupt is pending.
2:3 WRS Watchdog Reset Status
00 No Watchdog reset has occurred.
01 Core reset was forced by the watchdog.
10 Chip reset was forced by the watchdog.
11 System reset was forced by the
watchdog.
4 PIS PIT Interrupt Status
0 No PIT interrupt is pending.
1 PIT interrupt is pending.
5 FIS FIT Interrupt Status
0 No FIT interrupt is pending.
1 FIT interrupt is pending.
6:31
Reserved
0123456 31
ENW
WIS
WRS FIS
PIS
