Section 4 Sample Measurement
4-2.
4.1 Evaluation Measurement for the Receiver
The evaluation measurement procedure for the W-CDMA receiver is de-
scribed below.
Setup
Measurement procedure
[1] Set the frequency for the wanted signal source to the testing fre-
quency.
[2] Set the output level of the unit to the proper level for the input con-
nector of the receiver.
[3] Set the unit to W-CDMA modulation.
[4] Set the modulation parameter of the unit so that the receiver can re-
ceive the signal.
[5] Set the frequency for the noise signal source to that set in Step [1].
[6] Set the noise bandwidth for the unit to that wide enough for the
wanted signal.
[7] Set the calculated bandwidth for the unit to that for the wanted sig-
nal.
[8] Set the output level for the unit to the optimum level for the input
connector of the receiver. However, it should be higher by the noise
band calculation level.
[9] Measure the reception sensitivity of the receiver.
MG3681A + MU368040A + MX368041A/B
Two-signal coupler
Receiver
Wanted signal source
Noise signal source
MG3681A + MU368060A
MG3681A
Digital Modulation
Signal Genera tor
250kHz -3G Hz
3-6GHz (O ption)
Cancel
Set
RPP Reset
EditCursor
RF Output
Modulation
Function
On
Stby
Panel Lock
Local
Remote
Contrast
Preset
Knob Hold
Step
Resolution
Off
>○< On●
Frequency
Level
Memory
Digital Mod
Analog Mod
Config
%
Recall
Save
dB
Hz / fW deg / µV
-/+・0
BS
CE
Shift
CB
FEScreen Co
D
Display Of f/On
3
TTL
TTL
5
TTL
4
TTL
2
TTL
1
Digital Input
I/Q I nput / I/Q Output
I / Wide AM
50
Ω
50
Ω
Q
Output
InputI/Q Output
Pulse
TTL
F
600
Ω
600
Ω
FM/
φ
M
600
Ω
AM
50
Ω
Q
50
Ω
I
RF
50
Ω
!
Reverse Power
50W Max≦1GHz
25W Max
＞
1GHz
±50V DC Max
kHz/nW rad / mV321
MHz/mW ms / V654
GHz/dBm
s /dBµV987
Analog
Digital
F1
F2
F3
F4
F5
F6
Freq
3 000.000 000 00
MHz
Level
-123.15
dBm
IQ InputSymbol Clk
Clock
Data
Invrement
Step Value
Current
Frequency
Relative
On Off
Offset
On Off
Offset
Value
Frequency
Modulation Mode : I,Q Source :
Int
System : [PDC ]
Mod : π/4 DQPSK Bit Rate : 42.0 kbit/s
Filter : [RNYQ] α=0.50
Burst : [On]
Pattern : [UP TCH ]
Trigger : [Int]
Slot 0 Slot 1 Slot 2
UP TCH
△ △
MG3681A
Digital Modulation
Signal Genera tor
250kHz -3G Hz
3-6GHz (O ption)
Cancel
Set
RPP Reset
EditCursor
RF Output
Modulation
Function
On
Stby
Panel Lock
Local
Remote
Contrast
Preset
Knob Hold
Step
Resolution
Off
>○< On●
Frequency
Level
Memory
Digital Mod
Analog Mod
Config
%
Recall
Save
dB
Hz / fW deg / µV
-/+・0
BS
CE
Shift
CB
FEScreen Co
D
Display Of f/On
3
TTL
TTL
5
TTL
4
TTL
2
TTL
1
Digital Input
I/Q I nput / I/Q Output
I / Wide AM
50
Ω
50
Ω
Q
Output
InputI/Q Output
Pulse
TTL
F
600
Ω
600
Ω
FM/
φ
M
600
Ω
AM
50
Ω
Q
50
Ω
I
RF
50
Ω
!
Reverse Power
50W Max≦1GHz
25W Max
＞
1GHz
±50V DC Max
kHz/nW rad / mV321
MHz/mW ms / V654
GHz/dBm
s /dBµV987
Analog
Digital
F1
F2
F3
F4
F5
F6
Freq
3 000.000 000 00
MHz
Level
-123.15
dBm
IQ InputSymbol Clk
Clock
Data
Invrement
Step Value
Current
Frequency
Relative
On Off
Offset
On Off
Offset
Value
Frequency
Modulation Mode : I,Q Source :
Int
System : [PDC ]
Mod : π/4 DQPSK Bit Rate : 42.0 kbit/s
Filter : [RNYQ] α=0.50
Burst : [On]
Pattern : [UP TCH ]
Trigger : [Int]
Slot 0 Slot 1 Slot 2
UP TCH
△ △
