FX Series Programmable Controlers Applied Instructions 5
5-84
b) When n= 2, two sets of switches are read. This confi
uration requires 8 consecutive inputs
taken from the head address specified in operand S. The data from the first set of switches,
i.e. those usin
the first 4 inputs, is read into data device D
2
. The data from the second set
of switches (a
ain 4 di
its) is read into data device D
2+1
.
c) The outputs used for multiplexin
(D
1
) are
c
cled for as lon
as the DSW instruction is
driven. After the completion of one readin
, the
execution complete fla
M8029 is set. The
number of outputs used does
not
depend on
the number of switches n.
d) If the DSW instruction is suspended durin
mid-
operation, when it is restarted it will start from
the be
innin
of its c
cle and not from its last
status achieved.
e) It is recommended that transistor output units
are used with this instruction. However, if the
pro
ram technique at the ri
ht is used, rela
output units can be successfull
operated as
the outputs will not be continuall
active.
f) The DSW instruction ma
be used
ONCE
on
FX controllers with CPU versions lower than
3.07. FX units with CPU ver 3.07 or
reater and
all FX
2C
units can operate a maximum of
TWO
DSW instructions.
5.8.4 SEGD (FNC 73)
Operation:
A sin
le hexadecimal di
it (0 to 9, A to F)
occup
in
the lower 4 bits of source device S is
decoded into a data format used to drive a seven
se
ment displa
. A representation of the hex di
it
is then displa
ed. The decoded data is stored in
the lower 8 bits of destination device D. The upper
8 bits of the same device are not written to. The
dia
ram opposite shows the bit control of the
seven se
ment displa
. The active bits correspond
to those set to 1 in the lower 8 bits of the
destination device D.
Mnemonic Function
Operands
Program steps
SD
SEGD
FNC 73
(Seven
se
ment
decoder)
Hex data is
decoded into a
format used to
drive seven
se
ment displa
s
K, H
KnX, KnY, KnM, KnS,
T, C, D, V, Z
Note: Uses onl
the
lower 4 bits
KnY, KnM, KnS,
T, C, D, V, Z
Note: The upper 8 bits
remain unchan
ed
SEGD,
SEGDP:
5 steps
X0
Y10
Y11
Y12
Y13
M8029
Start of repetitive operation
Restart
Suspended
operation
Cycle complete
Y 10 D 0 K 1DSW X 10
M0
M8029
X0
RST
M 0
SET
M 0
X0
D 0 K2Y0SEGD
[ D ][ S ]
B0
B1
B2
B3
B4
B5
B6
It can be seen that
B7 is NOT used.
Hence B7 of the
destination device D
will alwa
s be OFF,
