FX Series Programmable Controlers Applied Instructions 5
5-58
The followin
points should be read while stud
in
the example on the ri
ht of the pa
e.
Please note, all normal rules associated with hi
h speed counters still apply.
The data table is processed one ‘record
number’ at a time, i.e onl
1 record is ever
active as the comparison data. The currentl
active record number is stored in data re
ister
D8130. As the comparison value for the active
record is ‘reached’, the assi
ned ‘Y’ device is
SET or RESET and the active ‘Record number’
is incremented b
1. Once all records in a data
table have been processed, the current record
pointer (D8130) is reset to 0 (the table is then
read
to process a
ain) and the operation
complete fla
M8131 is set ON.
If the hi
h speed counter is reset (b
pro
ram
or hardware input), when it resumes countin
and reaches the first record’s comparison value,
the M8131 fla
will be reset. Both the status of
M8131 and contents of D8130 are not editable
b
the user. If the DHSZ instruction is turned
OFF then all associated fla
s are reset.
Care should be exercised when resettin
the
hi
h speed counter or turnin
OFF the DHSZ
instruct as all associated ‘Y’ output devices will
remain in their last state, i.e. if an output was
ON it will remain ON until independentl
reset
b
the user.
The data within inactive records can be
chan
ed durin
operation allowin
data tables
to be updated. An
chan
e made is processed
at the end of the current pro
ram scan. The
HSZ instruction will continue to process onl
the
active data record, i.e. it will not reset due to the
updatin
of an inactive data record.
When the DHSZ instruction is initiall
activated it will not process a comparison until the
followin
pro
ram scan as the CPU requires a sli
ht time dela
to initialize the comparison
table.
321
432
543
654
765
Y10
Y37
ON
OFF
M8131
D8130 0 1 2 3 4 0
C251 - count value
equals HSZ
comparison value
C251 reset
M8000
K9999
M8130C251DHSZ D150
K5
C251
X17
