Technical Specifications
64-bit PowerPC processor architecture
•Virtual address range: 64 bits, or 18 exabytes
•Physical address range: 42 bits, or 4 terabytes
•Full 64-bit data paths and registers
•Native support for 32-bit application code
•64K L1 instruction cache; 32K L1 data cache
• 512K internal L2 cache
•Dedicated data flow for dividing one instruction into two internal operations
•Microcoded instructions for up to four internal operations
• Support for up to eight outstanding L1 cache line misses
•Hardware-initiated instruction prefetching from L2 cache
•Hardware- or software-initiated data stream prefetching; support for up to eight
active streams
•Maximum core frequency: 2GHz
Frontside bus
•Throughput: up to 8 GBps per processor
•Frequency: 1GHz DDR
•Width: 64-bit (32-bit in, 32-bit out) bidirectional
Wide execution core
• Support for up to 215 in-flight instructions
• In-order dispatch of up to five operations into distributed issue queue structure
• Simultaneous issue of up to 10 out-of-order operations:
– One Velocity Engine permute operation
– One Velocity Engine arithmetic logic operation
–Two floating-point operations
–Two fixed-point register-to-register operations
–Two load or store operations
– One condition register operation
– One branch operation
• Out-of-order and speculative issue of load operations
•Dual-pipeline 128-bit Velocity Engine for single-instruction, multiple-data
(SIMD) processing
•Two independent floating-point units for double-precision calculations
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White Paper
PowerPC G5
