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HD74AC182
Rev.2.00, Jul.16.2004, page 3 of 6
C
n + x
= G
0
+ P
0
C
n
C
n + y
= G
1
+ P
1
G
0
+ P
1
P
0
C
n
C
n + z
= G
2
+ P
2
G
1
+ P
2
P
1
G
0
+ P
2
P
1
P
0
C
n
G = G
3
+ P
3
G
2
+ P
3
P
2
G
1
+ P
3
P
2
P
1
G
0
P = P
3
P
2
P
1
P
0
Also, the HD74AC182/HD74ACT182 can be used with binary ALUs in an active Low or active High input operand
mode. The connections (Figure a) to and from the ALU to the carry lookahead generator are identical in both cases.
Carries are rippled between lookahead blocks. The critical speed path follows the circled numbers. There are several
possible arrangements for the carry interconnects, but all achieve about the same speed. A 28-bit ALU is formed by
dropping the last HD74AC182/HD74ACT182.
Truth Table
Inputs Outputs
C
n
G
GG
G
0
P
PP
P
0
G
GG
G
1
P
PP
P
1
G
GG
G
2
P
PP
P
2
G
GG
G
3
P
PP
P
3
C
n + x
C
n + y
C
n + z
G
GG
GP
PP
P
XHH L
LHX L
XLX H
HXL H
XXXHH L
XHHHX L
LHXHX L
XXXLX H
XLXXL H
HXL XL H
XXXXXHH L
XXXHHHX L
XHHHXHX L
LHXHXHX L
XXXXXLX H
XXXLXXL H
XLXXLXL H
HXL XL XL H
X XXXXHH H
X XXHHHX H
XHHHXHX H
HHXHXHX H
X XXXXLX L
XXXLXXL L
XLXXLXL L
LXLXLXL L
HXXX H
XHXX H
XXHX H
XXXH H
LLLL L
H : High Voltage Level
L : Low Voltage Level
X : Immaterial